Design and Analysis of Conventional CMOS and Energy Efficient Adiabatic Logic for Low Power VLSI Application
نویسندگان
چکیده
In recent years, low power circuit design has been an important issue in VLSI design areas. Adiabatic logics, which dissipate less power than static CMOS logic, have been introduced as a promising new approach in low power circuit design. energy. This paper proposes an Adder circuit based on energy efficient two-phase clocked adiabatic logic. A simulative investigation on the proposed 1-bit full adder has been implemented with the proposed technique and hence compared with standard CMOS, Positive Feedback Adiabatic Logic (PFAL) and Two-Phase Adiabatic Static Clocked Logic (2PASCL) respectively. Comparison has shown a significant power saving to the extent of 70% in case of proposed technique as compared to CMOS logic in 10 to 200MHz transition frequency range. Comparative results has also been shown by a histogram which represents the least power dissipation of proposed technique. In this paper all circuits are analyzed in terms of power using 0.35um technology and simulated using Pspice . Keywords—Adiabatic logic , energy recovery ,power supply ,low power ,Full adder ,Positive feedback adiabatic logic ,2PASCL
منابع مشابه
Comparative Analysis of Conventional CMOS and Energy Efficient Adiabatic Logic Circuits
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